Submitted by Nexus Technology on March 1, 2013 - 9:13am
3/5/2013 - Nexus Technology is proud to announce the MCA4000 Realtime Protocol Compliance and Bus Performance Analyzer. Nexus Technology's MCA4000 "Memory Compliance Analyzer" is a dual architecture instrument that has been designed and optimized for the task of DDR/LPDDR Protocol Compliance Analysis. The MCA4000 enables the detection of protocol violations plus the ability to acquire and analyze violations and bus performance.
Submitted by Nexus Technology on November 1, 2012 - 3:32pm
Optimal DDR4 validation requires analysis of the DDR4 signals, as seen by the memory components. This allows for the highest confidence that the signals captured are representative of the signals on the target. Nexus Technology scope component interposers allow for oscilloscope probing of the DDR4 signals extremely close to the memory components.
Submitted by Nexus Technology on November 1, 2012 - 3:24pm
DDR4 DIMM Slot Compliance Interposer allows access to all of the memory signals (except Data Bits, Check Bits and Strobes) and passes these signals onto the Logic Analyzer. Software is included to allow the user to acquire DDR4 Address and Control traffic from a DDR4 target.
Submitted by Nexus Technology on November 1, 2012 - 2:55pm
DDR4 Probe-Integrated Slot Interposers are designed for capture of DDR4 data rates of 2133MT/s or slower and may only be used with the Tektronix TLA7Bx4 acquisition modules. TLA configuration software is included to allow the user to acquire DDR4 2133MT/s Read AND Write data from a target.
Submitted by Nexus Technology on April 5, 2011 - 12:30pm
Beaverton, Ore., April 5, 2011 Tektronix, Inc., a leading worldwide provider of test, measurement and monitoring instrumentation, today announced availability of a complete DDR2 protocol debug and validation solution for the award-winning TLA6000 Series Logic Analyzers. The new options for the TLA6000 Series consist of everything embedded engineers - even those who are not DDR2 experts - need to validate and debug the operation of memory sub-systems in their designs.
DDR2 memory systems are used in many of today's embedded designs - commonly implemented as a bus on the microprocessor or as a block in an FPGA. The complexity of the DDR2 protocol and the number of command/data/address signals make it difficult to both visualize the operation of the bus and to isolate any potential problems. In addition, designers need to ensure that signal timing and interfaces comply with JEDEC standards. The new DDR2 options for the TLA6000 Series meet the emerging need for a more complete, easier to user DDR2 test solution at a more affordable price point.