NEX-PCIINTRx
PCI Interposer & Analysis Software
NEX-PCIINTRx was designed for PCI, 32- or 64-bit, 3.3V (NEX-PCIINTR3) or 5.0V (NEX-PCIINTR5) applications running 66MHz. The interposer board is an impedance controlled, matched trace length design that uses no active buffering. The analysis software for the logic analyzer provides clocking, setup and disassembly of PCI data.
NEX-PCIINTRx Interposer
The NEX-PCIINTRx interposer uses four Tektronix P6960 probes that are connected at right angles to the interposer. This reduces the keep-out volume required to use the interposer and allows the interposer to be used in systems with minimal clearance around the PCI cards. Please refer to the mechanical outline provided in this data sheet for details on the physical size of the NEX-PCIINTRx interposer. Please call for information on a PCI interface adapter that is not an interposer.
NEX-PCIINTRx Analysis Software
The included analysis software runs on the Tektronix Logic Analyzer. This software decodes bus transactions and displays information in easily understood text form, just like a typical Tektronix microprocessor disassembler. All PCI cycle types are identified. Class, Sub-Class, and Prog. I/F information is decoded to tell the user exactly what Class and Sub-Class of device is being accessed (mass storage, display, network, etc.). This information is also available in hexadecimal format. The command and status registers are also decoded and the bit-level information is displayed in an easy to read format. Invalid data bytes are dashed out during valid data cycles.
The disassembly software also has the ability to intelligently acquire PCI data. By taking advantage of the data clocking power built in to the Tektronix logic analyzer, the disassembly software can acquire only the PCI bus cycles and ignore Idle and Wait states. This allows the user to make optimum use of the acquisition card’s memory and see more bus transactions. For debug purposes the user also has the ability to override this function and acquire data on every PCI CLK rising edge to permit the user to see all of the bus traffic including the Idle and Wait states.
Logic Analyzer & Analysis Software Features
8GHz timing acquisition and low capacitive loading provide excellent timing analysis on every channel of the PCI bus.
Correlate other bus activity while the NEX-PCIINTR package is being used with a Tektronix logic analyzer to monitor the PCI activity by using other acquisition modules to monitor activity elsewhere within the system. The results of the two acquisitions can be correlated in time to determine the sequence of actions that occurred. For instance, the system microprocessor could be monitored and correlated with bus activity to verify CPU and PCI bus communication.
Setup and hold specifications can be verified, and margins tested, using the TLA600/700 Logic Analyzer. Each channel group (address, data, control, etc..) or individual channel can have a different setup time and hold time violation set as a fault trigger. If any individual channel or any channel in a group is ever in violation of the specified setup and hold time, the logic analyzer will stop and show the violation. The timing resolution of the acquired data at the violation point is 8GHz (125ps). Setup and hold margin testing can be done by altering the setup and hold times set for the violation trigger in 125ps increments. Changing these values until a violation occurs will show the actual setup and hold of the system under test.
Simultaneous State & Timing: The Tektronix TLA600/700 Logic Analyzer offers the unique capability of being able to acquire timing and state data through the same probes at the same time. For example, a user is able to view timing data acquired at 125ps resolution, with state data acquired synchronously (for instance, using NEX-PCIINTR5/3 custom clocking or clocking on every rising edge of CLK). This resolution gives the hardware designer the ability to easily determine edge relationships between any signal without having to deal with the inconvenience and loading problems that are inherent when forced to double-probe with individual state and timing acquisition cards.
System Requirements
- PCI 3.3 or 5.0V Applications
- TLA Application Software V4.2 or later
- One, 235MHz state speed (minimum), 136-channel acquisition module (TLA7Ax4)
- Four P6960 probes
- TLA Application Software V4.2 or later
Alternate configurations supported by this product may be found in the manual.
