NEX-DDR100P

DDR Interposer & Software

The NEX-DDR100P allows for acquisition of Address/Command, Read and Write Data of 100-pin, Unbuffered or Registered DDR 333 (or less) DIMMs. Supports PC1600/PC2100/PC2700 (DDR-200, DDR-266, DDR-333).

The NEX-DDR100P adapter is an impedance controlled, matched trace-length interposer design and does not require a dedicated slot. The logic analyzer connects above the normal DIMM height so that there is no interference with adjacent DIMMs.

Acquisition of DDR Address/Command, Read and Write data.

No added buffers to conceal system performance.

Impedance controlled / matched trace-length design.

8 GHz Timing analysis available on all DDR signals.

Correlation with data from other acquisition modules.

Oscilloscope Connectivity to any channel without having to re-probe via the TLA’s Enhanced iView Analog Mux capability.

Selective Clocking stores data when Commands are present and for thirteen clock cycles after Column Address assertion, resulting in more DDR Bus Cycle activity and fewer Idle cycles stored in acquisition memory.

Simultaneous state and timing on every channel of the TLA.

Pre-defined Symbols for easy Trigger Setup for the following Command Cycles: Read Col Address Read, Write Col Address Write, Mode Register Set, Row Address Strobe, No Operation, Ignore Command Data, Burst Stop, Refresh, Precharge, and Precharge Select Bank.

System Requirements

• DDR 333MT/s Read and Write Acquisition Requires
  • TLA Application Software V4.2 or later
    • One 450MHz state speed acquisition module (TLA7AA4 or TLA7AB4)
      • Four P6860 probes

More detailed information can be found in the manual.

Ordering Information

Please send quote requests to quotes@nexustechnology.com. Purchase orders can be faxed to 877-595-8118.

All prices are US dollars only. We accept Visa, MasterCard, American Express and JCB. NET30 terms are available for established accounts.