DDR2-400 DIMM Slot Interposer

The logic analyzer setup software (Tektronix refers to these as 'Support Packages') provides a quick setup of the logic analyzer channels and logic analyzer clocking/acquisition parameters. This software also provides protocol decoding of the DDR2 transactions for easy display and logic analyzer triggering/filtering. These products also include Nexus Technology's Selective Clocking Feature - a transparent clocking option enabling filtering of DDR2 idle sequences to conserve logic analyzer memory.

In order for the logic analyzer to capture data, the DDR2 signals must be digitized. For the command and address bus, this process is relatively straightforward as the center of the valid data eyes align with rising edge of the DDR clock. For the DDR2 data bus signals, the process of determining the optimal sample position for digitization is much more complicated. The valid eyes are purposely skewed - as per the DDR2 specification - on a byte basis relative to the DDR clock. The valid eyes also contain skew (again relative to the DDR clock) on a bit basis due to unavoidable artifacts of high-speed designs and the timing variations caused by the digitizing of the signals based on the threshold.

These, among other factors, make reliable and accurate DDR2 read and write data bus acquisition extremely difficult - if done manually.NEX-DDR2-SPA automates this process enabling quick and reliable DDR2 read and write data bus acquisition in only minutes. For more information, please see the NEX-DDR2-SPA product page.

There's a BIG difference between protocol decode and protocol violation analysis. Protocol decoding provides a static tabulation of command and address bus activity. This functionality is made available through the logic analyzer listing window using a Nexus Technology DDR2 support package/setup software. Performing a very different and powerful set of tasks, protocol violation analysis analyzes the entire logic analyzer memory, compiling statistical information and error reporting based on every command acquired.

This provides a global picture of the activity on the bus and - more importantly - analyzes every command to see that the protocol adheres to the JEDEC specification. Protocol violation analysis software is available for all DDR2 Interposers. Please see theNEX-DDR-PROTOCOL product page for more information.

The logic analyzer setup software (TLA support package) included with this package acquires/reconstructs the 400MHz command/address bus and acquires/reconstructs the 800MT/s read write data from the data bus. The software also decodes and displays the bus protocol, shows the valid read/write data and provides easy DDR protocol triggering to quickly capture relevant data.

These products also come with the NEX-DDR-PROTOCOL software tool. This software provides statistical information and global bus activity to quickly give the user an overview of the DDR2 bus activity without having to revert to a listing or waveform window. The software also performs basic protocol violation checking. Advanced protocol violation checking is available for purchase separately. Please see the NEX-DDR-PROTOCOL product page for more information on this powerful tool.

Nexus Technology has designed this interposer to have a minimal effect in your target. As with any interposer solution, approximately one inch of trace length will be added between your target and the DIMM. Depending on the target layout, memory controller, DIMM type and DIMM socket being probed, an interposer may affect the performance of your system. All users are given 30 days to qualify the interposer in their system. Should performance issues arise it is important to know that alternate solutions are available. Nexus Technology offers NEXVu VDIMMs which provide both optimal probe points (at the memory components) and no added trace length or interposer effects. Also available are memory component products which also provide optimal probe points, extremely small added trace lengths, and extremely small interposer effects.