DDR4 DIMM Slot Probe Integrated Interposer
- 288-pin DIMM Slot Interposer
- 284 pin version also available
- High Speed DDR4 Debug, Validation, & Compliance
- Designed for DDR4-3200+ *
- High impedance, oscilloscope quality probing
- SiGe hybrid ASIC analog compensation
- Scope Probe Per Signal functionality when combined with a Tektronix LA's unique Analog Mux Capability
- Automated Logic Analyzer Setup
- Optional DDR4 Compliance Analysis
- Leverages proven, Industry leading, DDR3 DIMM Interposer technology
- Compatible with Nexus MA4100 Series Memory Analyzer
* The Tektronix LA supports State, MagniVu and iCapture up to 2800+. The MA4100 cross-triggering enables supports MagniVu and iCapture up to 3000+
Nexus Technology recommends DDR4 slot interposers for applications where the customer must have the greatest flexibility for probing of different DDR4 DIMMs. This interposer is an extender design and does not require a dedicated DIMM slot. The logic analyzer connects above the standard DIMM height so that there is no mechanical interference with adjacent DIMMs.This is a passive interposer with no added buffers to conceal system performance.
This DDR4 DIMM slot interposer comes with logic analyzer setup software, DDR4 command sequence decode software, DDR4 data eye sample point analysis software, and optionally comes with command sequence & timing compliance software.
The logic analyzer setup software (Tektronix refers to these as 'Support Packages') provides a quick setup of the logic analyzer channels and logic analyzer clocking/acquisition parameters. This software also provides protocol decoding of the DDR4 transactions for easy display and logic analyzer triggering/filtering.
A powerful analog validation feature is the Tektronix Logic Analyzer's Analog Mux capability. This provides the ability to see any channel of the DDR4 bus in seconds on an oscilloscope. This is invaluable information which allows analysis within minutes as to the status and behavior of the DDR4 bus. No extra probing is required to gain analog incite of the DDR4 bus. This information can be pushed back into the logic analyzer software and viewed in a wave form window along with the state or timing data using the iView Feature.
Tektronix discusses some of these topics in more detail in the application note, Debugging Timing Problems with a Logic Analyzer.
Logic analyzer setup software (TLA support package) included with this product acquires/reconstructs the command/address bus and acquires/reconstructs the read/write data from the data bus. The software also decodes and displays the bus command sequence, shows the valid read/write data and provides easy DDR command sequence triggering to quickly capture relevant data.
The optional DDR4 Memory Compliance Analysis package enables and automates measurement of the DDR4 bus activity for fast and easy functional testing and extensive compliance, statistical, and performance analysis.
These products optionally include the DDR4 Memory Compliance Analysis software package. This software package performs advanced command sequence & timing compliance analysis. It also provides statistical information and global bus activity to quickly give the user an overview of the DDR4 bus activity without having to revert to a listing or waveform window.
- Extensive JEDEC DDR4 Compliance Analysis
- Quick and Easy Setup w/No Calibration Required
- Automated Acquisition and Measurement
- Powerful in-application graphical and tabular analysis results
- Memory controller & JEDEC parameters predefined
- Quickly navigate through multiple acquisitions
The DDR4 specification calls out skew on a the DQ data bus on a per byte basis, relative to the DDR clock. Design of high speed interconnect will also introduce skew on a per bit basis. In order for the logic analyzer to capture data accurately, the sample points must be set in consideration of this byte to byte and bit to bit skiew. When the data bus activity is inadequate for automated sample setting, iCiS can be used to graphically display the signal eyes on a per group or per signal basis, and then graphically select the optimum sample point voltage threshold and timing offset
Passive Module Reduction (MR) Technology™
Nexus Technology's Module Reduction Technology™ is available with select DDR3 products. This technology allows for full acquisition including command, address, read and write data while cutting the Tektronix logic analyzer module requirement in half. The number of TLA7BB4 modules required for DDR3 >1333 acquisition is reduced from four to two when using MR Technology™. When feasible, the number of TLA7BB4 modules required for DDR3-1333 or slower acquisition is reduced from two to one when using MR Technology™
Module Reduction Technology™ is a software solution. No qualifier sideband signals are required and no active circuitry is implemented in MR Technology™ which would otherwise force double-probing and increase the load on the DDR3 target.
|Acquisition||Mainframe Required||Module(s) Required||Probes Required|
|Cmd/Address Read; Data Read and Write||TLA7000 Series||2 - TLA7BB4 1.4GHz||
Product Configuration Table
|Nomenclature||Nexus Probes Included?||Pin Count||Nexus Hardware Included||Nexus Software Included|
|NEX-DDR4INTR-XL||Yes 1||284 Pin||1 - DDR4 DIMM Slot Interposer||
|NEX-DDR4INTR288-XLT||Yes1||288 Pin||1 - DDR4 DIMM Slot Interposer||
Note 1 - Probes are preattached to interposer