DDR3 Compliance Analysis Software for Tektronix Logic Analyzers

DDR3 Memory Compliance Analysis Software

For Tektronix Logic Analyzers

Demo version of software available. Please contact us for a copy.

The DDR3 Memory Compliance Analysis package enables and automates measurement of DDR3 bus activity for fast and easy functional testing, and extensive compliance, statistical, and performance analysis.

  • Easily correlate with other buses or memory channels
  • Extensive JEDEC DDR3 compliance analysis
  • Quick and easy setup with no calibration required
  • Ultra-fidelity interconnects insure passive connection to your system
  • Automated acquisition and measurement for analysis of intermittent or infrequent events
  • Test up to two, fully loaded, quad-rank memory channels
  • Compare and correlate to other buses (e.g. PCIe) or memory channels
  • DDR3-2400 / DDR3-2133 / DDR3-1866 / DDR3-1600 / DDR3-1333 / DDR3-1066 / DDR3-800 / DDR3-CUSTOM

JEDEC DDR3 Compliance Analysis

  • Flexible and easy to configure
  • Analysis of over 43 JEDEC compliance parameters
  • Includes Power-up/-down and self-refresh analysis
  • Includes auto-precharge (RDA/WRA) analysis
  • Standard and non-standard JEDEC SDRAM(s) up to DDR3-2433
  • Test up to two, fully loaded, quad-rank memory channels
  • Powerful in-application graphical and tabular analysis results
  • HTML reporting
  • XML exporting for offline processing
Compliance Parameters
CMD w/sREF Rank MRS Settle SRE w/S sSREF Time
SRE w/sACT Rank WR Burst MRS w/sACT Rank RD to WR(A) Separation
RD(A)/WR(A) during MRS PDX Slow Exit CMD w/sPD Rank Rank DLL Reset to RD(A)
RD(A)/WR(A) w/sREF Bank RD Burst REF w/sACT Bank sPD Time Min.
RD(A)/WR(A) to sPRE Bank sPD Time Max. PRE(A) Rank Settle PRE(A) Bank Settle
REF Before SRE sACT Time Min. SRE Separation from PRE(A) sACT Time Max.
SRE Separation from REF ACT to RD(A)/WR(A) SRE Separation from ACT RD to PRE(A)
SRE Separation from MRS RD to ACT SRE Separation from WR WR to PRE(A)
SRE Separation from WRA WR to ACT SRE Separation from RD(A) CKEx Signal After DLL Reset

Quick Setup & Automated Acquisition

Quick setup, automated analysis, and zero calibration provide results extremely quickly.

  • Zero calibration needed
  • Build custom test runs to zero in on compliance issues
  • Automated acquisition
  • Automated analysis
  • Memory controller & JEDEC parameters predefined

Performance & Statistical Analysis

Extensive compliance, statistical, and performance analysis information are displayed in tabular and graphical displays. Exporting of data is also available for customized analysis. The metrics covered include:

  • Data bus performance
  • Rank / Bank / System Utilization
  • Actual transfer rate measurements
  • Compliance summaries with margins
  • Error (timing violation) reporting

Detailed Data at Your Fingertips

In addition to performance/statistical analysis and automated acquisition, detailed analysis results are also available for all acquisitions in a test run as well as all the acquired data from all acquisitions in a test run.

  • Quickly navigate through multiple acquisitions
  • Zero in on compliance problems right inside a waveform or listing window
  • Listing and waveform windows with compliance violations built in
  • Add cursors, jump to violations, see min/max measurements, lock data windows and more!
  • Multi-acquisition data management

Ultra-Fidelity Interconnects

  • DIMM Interposers
    • DDR3-2400 with slower or custom rates supported
    • Full slot w/72-/64-bit DQ data
    • Command/Control/Address dedicated
    • Second Slot Probing
  • SODIMM Interposers
    • DDR3-2133 with slower or custom rates supported
    • Full slot w/64-bit DQ data
    • Full slot w/72-bit data (ECC spec)
    • Command/Control/Address dedicated
    • Second Slot
  • Component Interposers
    • DDR3-2133 with slower or custom rates supported
    • x4/x8/x16
    • All device densities
  • miniDIMM Interposers
    • DDR3-1600 with slower or custom rates supported
    • Full slot w/72-/64-bit DQ data
  • Embedded direct probing
    • DDR3-2133 with slower or custom rates supported

General Information

Specification Detail
Interface Type Varies
JEDEC Interfaces DDR3 SDRAM DIMMs, SODIMMs, miniDIMMs, components, or direct/custom probing
JEDEC Modules Supported PC3-19200, PC3-17000, PC3-14900, PC3-12800, PC3-10600, PC3-8500, PC3-6400
DDR3 Data Rates Supported (MT/s) 2400, 2133, 1866, 1600, 1333, 1066, 800

Tektronix Recommended Hardware

Specification Detail Quantity
Logic Analyzer Series TLA7000 (TLA7016 or TLA7012) -
Logic Analyzer Module(s) TLA7BB2/3/4 1 *Note 1
Logic Analyzer Probes NEX-PRB1XL 1 *Note 2

Product Configuration

Brief Description Nomenclature Detail
DDR3 Memory Compliance
Analysis Software		 NEX-MCATLA-DDR3-SWL
  • 1- DDR3 Memory Compliance Analysis Package for TLA Single User License

Note 1: The number of channels required or the number of modules may be two depending on the interconnect and data acquisition capabilities needed. All cmd/addr/ctrl acquisition required for DDR3 Memory Compliance Analysis can be accomplished with one TLA7BB2 (68-channel) module.

Note 2: More than one probe of the same or different type may be needed for DQ data acquisition depending on configuration.

More Information

Demo Software
Demo version of software available. Please contact us for a copy.
Presentation
Product Presentation coming soon.
Datasheet
Product datasheet in PDF format.
Manual
Please contact us.
Ordering Information
Please send quote requests to quotes@nexustechnology.com. Purchase orders can be faxed to 877-595-8118.