NEX-80200 (XScale)

The NEX-80200 Disassembly Support provides clocking, setup, and disassembly of the 80200 microprocessor when used with the 80312 I/O companion chip. NEX-80200 is software only. Specific wiring must be followed if the 80200/80312 signals are routed to Mictor connectors for interface to the TLA600 or 700 Logic Analyzer. Please refer to the NEX-80200 Data Sheet below for more information. If a connector is not designed into the target a general purpose probe adapter must be used.

Intel 80310 "Cyclone" Evaluation Board Support: 80310 support requires the use of one NEX-HDSWIZ adapter available from New Wave. Please call for details on the wiring of the NEX-HDSWIZ.

Disassembly Features

Identification / Support of the following

  • RAS/CAS Address Reconstruction (from 80312 I/O Companion Chip)
  • Architecture v4 Level Instructions and Addressing modes
  • Display of SDRAM Cycles Only, SDRAM Cycles and StrongArm Instructions or StrongArm Instructions Only.
  • SDRAM Read Latency of 2 and 3.
  • Memory Configurations SA[12:0] and SA[13,11:0]

Support for the following 80200 modes

  • Read Latency of 2 or 3, SA[12:0] or
  • SA[13,11:0] Address format.

Physical Address Reconstruction
The 80200 microprocessor and 80312 I/O companion chip combination uses SDRAM for code execution memory. However, because SDRAM is accessed by Row and Column address cycles it becomes necessary to translate those two cycles into a physical address equivalent which is necessary for tracking the flow of program code. The Address group is used by the 80200 support to reconstruct the physical address from Row and Column information contained in the DRAMAddr group. The DRAMAddr group in the 80200 support is configured by default for SA[12:0] Address format. The disassembler also supports SA[13,11:0] Address format. These settings determine how the Physical address is reconstructed into the Address display group. For more information on SDRAM Memory configurations and Address formats, refer to the “Intelâ 80312 I/O Companion Chip Developer’s Manual”, Section 3.2.3 “SDRAM Memory Support”.

SDRAM Read Latency
The 80312 I/O companion chip memory controller supports SDRAM Memory with Read Latency of 2 or 3 clock cycles. The disassembly software includes a select field to enable the user to inform the software of this latency, insuring accurate disassembly.

Cycle Display Control
The data acquired from the 80312 SDRAM interface consists of raw SDRAM cycles. This information can be viewed by setting the Cycle Display mode to “SDRAM Only”. The NEX-80200 disassembler first reconstructs the data cycles from the SDRAM activity. The resulting read cycles have their addresses reconstructed and are then passed to the next level, which disassembles the XScale Instruction Set. The XScale Instructions can be view alone by setting the Cycle Display mode to “StrongArm Only”. If, for any reason, both the SDRAM and XScale information is relevant, the Cycle Display mode can be set to “SDRAM/StrongArm”. Changing the standard Tektronix LA “Show” mode to “Software” also is available to suppress idle cycles.

All five addressing modes are supported:

Addressing Mode 1

  • Shifter operands
  • Immediate
  • Register
  • Logical shift left by immediate
  • Logical shift left by register
  • Logical shift right by immediate
  • Logical shift right by register
  • Arithmetic shift right by immediate
  • Arithmetic shift right by register
  • Rotate right by immediate
  • Rotate right by register
  • Rotate right with extend

Addressing Mode 2

  • Immediate offset
  • Register offset
  • Scaled register offset
  • Immediate pre-indexed
  • Register pre-indexed
  • Scaled register pre-indexed
  • Immediate post-indexed
  • Register post-indexed
  • Scaled register post-indexed

Addressing Mode 3

  • Immediate offset
  • Register offset
  • Immediate pre-indexed
  • Register pre-indexed
  • Immediate post-indexed
  • Register post-indexed

Addressing Mode 4

  • Increment after
  • Increment before
  • Decrement after
  • Decrement before

Addressing Mode 5

  • Immediate offset
  • Immediate pre-indexed
  • Immediate post-indexed

Timing Analysis
By acquiring data in asynchronous mode on the Tektronix Logic Analyzer, high speed accurate timing measurements can be made of the 80200 up to 2Ghz (500 ps) using a Tek TLA600 or 700 system.

Correlating Bus Activity
While the NEX-80200 package is being used to monitor the 80200 activity, another acquisition module can be used to monitor activity elsewhere in the system. The results of the two acquisitions can be correlated in time to determine the sequence of actions that occurred. For instance, a PCI bus could be monitored and correlated with the 80200 activity.

LAs Supported / Channel Count Requirement
TLA600/700 Support (Can be used with TLA7L/M/N/P or Q cards)DAS9200 & TLA500 (92A96/C96) Support Prism 3000 32 GPX Support TLA700 Channels Required Notes
Y N N 136 80200 S/W only support