NEX-PXA2XX
- Quick setup of the Tektronix Logic Analyzer
- Disassembly of the acquired PXA210/250 data acquired from the SDRAM interface
- Support included for the Intel BBPXA2XX Evaluation Board and the WindRiver PXA2XX Development Board
- Custom clocking or clock on every edge
- Up to 8GHz timing acquisition on every channel (dictated by the Tektronix acquisition module used)
The NEX-PXA2XX support software acquires and decodes PXA2XX bus activity and displays the information as assembly language mnemonics (machine code). This permits the tracing of code execution for debug purposes. It is also possible to filter the data display cycle types of interest to the software engineer. The user can choose to display the acquired data in Hardware, Software, Control Flow, or Subroutine modes. Every stored cycle has a timestamp value stored with it. This time information, accurate to 500ps in the TLA7L/M/N/P/Q series, and accurate to 125ps in the TLA7AA/B series, permits precise measurements of microprocessor bus activity. Because of the design of Tektronix Logic Analyzers there is no need to worry about trading off acquisition memory depth when making these measurements, as the timestamp memory is separate from the acquisition memory.
System Requirements
TLA600 or TLA700 with an acquisition card width of 102- or 136-channels. The state clock speed of the TLA600 or TLA700 acquisition card must meet or exceed the SDRAM bus clock rate of the target. TLA Application software V3.2 or later is also required.
