Compliance analysis performed after or alongside electrical (analog) analysis and consists of: logic (command transfer) verification and timing margin analysis to JEDEC timing specifications. This ensures your target is compliant with JEDEC specification timing requirements and must be done in real time or violations can be missed. Knowing that a violation occurred is a start but the ability to capture bus cycles leading up to the violation and following the violation provides powerful insight into the cause and result of the violation. A memory analyzer is used for compliance analysis. It not only addresses the needs described above but also provides insight into the analog characteristics of all bus signals.
Memory Analyzer Instruments
|MA5100 Series Memory Analyzer||Memory analyzer supporting LPDDR4 and LPDDR3 performance, margins and capture up to LPDDR4-4267 (2.4GHz) and LPDDR3-2133 (2.4GT/s capable) with 1G-Sample acquisition depth, ClockSafe™ and Sixteen Smart Frequency Analysis.|
|MA4100 Series Memory Analyzer||Memory analyzer supporting DDR4 and DDR3 performance, margins and capture up to DDR4-3200 (1.6GHz) and DDR3-2133 (1.6GT/s capable) with 1G-Sample acquisition depth.|
Compliance analysis also requires high fidelity interposers and probes that provide access to your target. A complete solution from interposer to compliance instrument focused on your target application insures accurate compliance validation for leading edge memory technologies.
Memory Analyzer Interposers
|DDR4 Main Memory Interposers||See all available interposers for DDR4 memory.|
|See all available interposers for LPDDR4 memory.|
|See all available interposers for DDR3 memory.|
|See all available interposers for LPDDR3 memory.|