No matter where you are in your product development cycle we have you covered! Complete analysis and validation of your product design, power-on, debug, compliance and optimization.
- Electrical Analysis– (Early simulation, power on analog debug and analysis)
- Logic Acquisition– (State/Cycle analysis viewing multiple signals as Commands and Data )
- Compliance Analysis– (Real Time bus protocol and performance analysis compared to JEDEC standards. System Optimization)
Product analysis and validation starts by examining the analog characteristics of the signals on your memory bus using an oscilloscope. Signal integrity, Jitter and Drift are looked at and augmented with compliance software used on the oscilloscope that automates the memory compliance verification. However, as clock rates increase and memory components shrink with smaller pitches and Package on Package (PoP) that places the memory component on top of the SOC, gaining access to the signals is a major hurdle that must be overcome. High fidelity interposers that break out the signals at the memory component must Read more…
The analog characteristics have been validated and it’s time to move on to cycle based analysis. Visibility of commands such as Read and Write with their associated data is acquired and analyzed for accurate bus transactions. A Logic Analyzer or Memory Compliance Analyzer is typically used to acquire dozens or hundreds of signals and software is provided that displays the acquired signals as commands and data.
Compliance / Logic Analysis
The target is running and the analog characteristics have been verified and command transfers are proven. It is critical that verification is done to insure the target is meeting JEDEC standards/requirements. All violations must be verified simultaneously in real time to assure you have complete analysis and have not missed anything. A Memory Analyzer (MA) is used for compliance validation. An MA is not simply a protocol analysis tool. A compliance analyzer must… Read more…